Xilinx MPSoC PL Reset

Tags: mpsoc xilinx

When the PL reset is enabled in the IP Integrator, the pin used is one of the EMIO pins:

PL Reset 0 => EMIO 95
PL Reset 1 => EMIO 94
PL Reset 2 => EMIO 93
PL Reset 3 => EMIO 92

From the Zynq Ultrascale+ Technical Reference Manual, p. 769:

Up to four outputs for GPIO[92:95] can act as reset signals to user-defined logic in the PL. The number of GPIO EMIO signals depends on the number of PL fabric resets selected in the Vivado PS configuration wizard (PCW). For example, if one reset is selected, GPIO[95] is assigned as a reset signal. If two are selected, then GPIO[95:94] are assigned

The data register for GPIO Bank 5 (which contains these EMIO pins) is located at address 0xFF0A0054 (see Xilinx MPSoC Register Reference). This is a 32-bit register corresponding to EMIO[95:64].

Also see AR #68962.